1. Field of the Invention
The present invention relates to package structures and fabrication methods thereof, and more particularly, to a stack-type package structure and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. Current chip packaging technologies have developed various types of flip-chip packaging modules such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM) packages.
In a flip-chip packaging process, a big CTE (Coefficient of Thermal Expansion) mismatch between a chip and a substrate adversely affects the formation of joints between conductive bumps of the chip and corresponding contacts of the substrate and easily causes delamination of the conductive bumps from the substrate. Further, along with increased integration of integrated circuits, the CTE mismatch between the chip and the substrate induces more thermal stresses and leads to more serious warpage, thereby reducing the reliability of electrical connection between the chip and the substrate and resulting in failure of a reliability test.
Accordingly, an interposer made of a semiconductor material is provided between the substrate and the chip to form a semiconductor stack structure. Since the interposer is close in material to the chip, the above-described drawbacks caused by a CIE, mismatch can be effectively overcome.
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor stack structure 1. Referring to FIG. 1, a silicon interposer 10 is disposed between a packaging substrate 18 and a semiconductor chip 11. The silicon interposer 10 has a plurality of through silicon vias (TSVs) 100 and an RDL (redistribution layer) structure 15 formed on the TSVs 100. The RDL structure 15 of the silicon interposer 10 is electrically connected to bonding pads 180 of the packaging substrate 18 through a plurality of conductive elements 17. The bonding pads 180 of the packaging substrate 18 have a large pitch therebetween. Further, an adhesive material 12 is formed to encapsulate the conductive elements 17. The TSVs 100 of the silicon interposer 10 is electrically connected to electrode pads 110 of the semiconductor chip 11 through a plurality of solder bumps 19. The electrode pads 110 of the semiconductor chip 11 have a small pitch therebetween. Further, an adhesive material 12 is formed to encapsulate the solder bumps 19.
The 3D semiconductor stack structure 1 having the silicon interposer 10 overcomes the above-described drawbacks caused by a CIE, mismatch and has a reduced size. For example, a substrate generally has a minimum line width/pitch of 12/12 um. When the I/O count of a semiconductor chip increases, since the line width/pitch of the substrate cannot be reduced, the area of the substrate must be increased such that more traces can be formed on the substrate and electrically connected to the semiconductor chip. On the other hand, referring to FIG. 1, the semiconductor chip 11 is disposed on the silicon interposer 10 having TSVs 100 and electrically connected to the substrate 18 through the silicon interposer 10. Since the silicon interposer 10 has a line width/pitch of 3/3 um or less, the area of the silicon interposer 11 is sufficient for electrical connection with the semiconductor chip 11 having a high I/O count and hence the area of the substrate 18 does not need to be increased. Further, the fine line width/pitch of the silicon interposer 10 facilitates to shorten the electrical transmission path. Therefore, the semiconductor chip 11 disposed on the silicon interposer 10 achieves a higher electrical transmission speed than if being directly disposed on the substrate 18.
However, the 3D semiconductor stack structure 1 having the silicon interposer 10 has a high fabrication cost. Accordingly, Silicon-less interconnect technology has been developed to fabricate packages that do not include silicon interposers and have a size less than the 3D semiconductor stack structure. FIGS. 2A to 2C are schematic cross-sectional views showing a method for fabricating such a package structure.
Referring to FIG. 2A, a first dielectric layer 21 is formed on a carrier 20 and has a plurality of openings exposing portions of the carrier 20. Then, a circuit sub-layer 22 is formed on the first dielectric layer 21. Thereafter, a second dielectric layer 23 is formed on the first dielectric layer 21 and the circuit sub-layer 22 and has a plurality of openings exposing portions of the circuit sub-layer 22. Subsequently, a plurality of conductive bumps 24 are formed in the openings of the second dielectric layer 23 and electrically connected to the circuit sub-layer 22.
Referring to FIG. 2B, a semiconductor chip 25 is disposed on the conductive bumps 24, and an underfill 26 is formed between the semiconductor chip 25 and the second dielectric layer 23. Then, an encapsulant 27 is formed on the second dielectric layer 23 for encapsulating the semiconductor chip 25 and the underfill 26.
Referring to FIG. 2C, the carrier 20 is removed to expose portions of the circuit sub-layer 22. Then, a plurality of conductive elements 28 are formed on the exposed portions of the circuit sub-layer 22. As such, a small-sized package structure without a silicon interposer is obtained. The package structure can further be electrically connected to an external electronic element through the conductive elements 28.
However, since an external electronic element such as a circuit board, a packaging substrate or a printed circuit board can only be disposed on a lower side of the package structure (i.e., the side having the conductive elements 28), the functionality of the package structure is extremely limited and the end application of the package structure is greatly reduced. As such, the package structure cannot meet the requirement of current end products.
Therefore, there is a need to provide a package structure and a fabrication method thereof so as to overcome the above-described drawbacks.